Semiconductor processing is an increasingly complex and mature technology for which the cost of test and burn-in consumes an ever larger share of production costs. Continuous progress is being made in semiconductor technology and wafer fabrication efficiency, such progress being characterized by Moore's law which has successfully predicted a doubling of the number of devices on a semiconductor chip every two years. Productivity gains from advances in semiconductor technology and wafer fabrication efficiency underlie the modern economy, making possible mobile electronics, internet communications and much of modern life. However, semiconductor packaging and testing have not maintained the same pace of technological progress.
Methods commonly used for contacting individual, separated semiconductor chips during testing have remained largely the same for decades. For example, after wafer probe testing, a wafer is sawn apart into individual chips. Additional packaging steps may be used to protect the chip and facilitate its attachment into an electronic system. After packaging, each chip is inserted into a first socket to test for opens and shorts before burn-in. Each chip is then released from the first socket and transported in a tray. In an optional next step, the chip is inserted into a second (burn-in) socket and burned-in for eight hours at an elevated temperature of about 125° C. After burn-in, the chip is removed from the burn-in socket and transported in a tray to “final test” where it is inserted into a third socket. A comprehensive set of tests is done in final test, which tests are typically done at several speeds and temperatures. The socketing, sockets, fixtures, test boards and handling involved with the process of testing individual chips and other microelectronic devices is an increasing problem in streamlining the production of semiconductor devices.
After appropriate burn-in and test, devices may be juxtaposed and joined together in a stack to form a compact microelectronic device. Handling, testing and joining bare semiconductor chips has proven to be difficult. Alignment of individual devices to an accuracy suitable for contacting and joining at elevated temperatures is a barrier to efficient stacking of complex devices that require extensive testing. One approach to the problem is to burn-in and test chips in wafer form before singulation into individual dice; the tested wafers are then stacked in registration, joined together and diced into individual stacked devices. Full wafer stacking suffers from an inefficiency in that a wafer typically contains a significant percentage of defective chips that, when joined with other chips into a stack, cause the entire stack to be defective. A more effective way is needed to handle and align individual chips so that only known good dice (KGD) are stacked to form a fully functioning microelectronic device.
Another approach involves placing chips, whether packaged or not, in an accurately positioned array on a carrier for purposes of testing. To provide accurate placement of chips on the carrier (accurate placement is needed for registering terminals on the chips to mating contactors), each chip must be loaded onto the carrier precisely. Accurate registration ensures that pads of a device reliably and repeatedly contact corresponding pads of the tester. After fully testing the chip, it must be removed from the carrier and placed in accurate juxtaposition to other chips to be joined into a stacked device. More efficient methods for handling, testing and aligning chips for joining is needed for the advancement of the semiconductor art to higher density electronics.